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1. general description the pcf85134 is a peripheral device which interfaces to almost any lcd 1 with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 60 segments. in addition, the pcf85134 can be easily cascaded for larger lcd applications. the pcf85134 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized using display ram with auto-incremented addressing, hardware subaddressing, and display memory switching (static and duplex drive modes). 2. features n single-chip lcd controller and driver n selectable backplane drive con?gurations: static, 2, 3, or 4 backplane multiplexing n 60 segment outputs allowing to drive: u 30 7-segment alphanumeric characters u 16 14-segment alphanumeric characters u any graphics of up to 240 elements n cascading supported for larger applications n 60 4-bit display data storage ram n wide lcd supply range: from 2.5 v for low threshold lcds up to 6.5 v for guest-host lcds and high threshold twisted nematic lcds n internal lcd bias generation with voltage follower buffers n selectable display bias con?gurations: static, 1 2 , or 1 3 n wide logic power supply range: from 1.8 v to 5.5 v n lcd and logic supplies may be separated n low power consumption n 400 khz i 2 c-bus interface n compatible with any microprocessor or microcontroller n no external components required n display memory bank switching in static and duplex drive mode n auto-incremented display data loading n versatile blink modes n silicon gate cmos process pcf85134 universal lcd driver for low multiplex rates rev. 01 17 december 2009 product data sheet 1. the de?nition of the abbreviations and acronyms used in this data sheet can be found in section 17 .
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 2 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 3. ordering information 4. marking table 1. ordering information type number package name description delivery form version pcf85134hl/1 lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm tape and reel sot315-1 table 2. marking codes type number marking code pcf85134hl/1 pcf85134hl
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 3 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 5. block diagram fig 1. block diagram of pcf85134 013aaa204 lcd voltage selector clock select and timing blinker timebase oscillator input filters i 2 c-bus controller power-on reset clk sync osc scl sda backplane outputs display control bp0 bp1 bp2 bp3 display segment outputs display register output bank select and blink control 60 s0 to s59 sa0 v dd a0 a1 a2 pcf85134 lcd bias generator v ss v lcd command decode write data control display ram data pointer and auto increment subaddress counter
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 4 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 6. pinning information 6.1 pinning top view. for mechanical details, see figure 22 . fig 2. pin con?guration for sot315-1 (pcf85134) pcf85134 s31 s10 s32 s9 s33 s8 s34 s7 s35 s6 s36 s5 s37 s4 s38 s3 s39 s2 s40 s1 s41 s0 s42 v lcd s43 v ss s44 sa0 s45 a2 s46 a1 s47 a0 s48 osc s49 sync s50 v dd s51 s30 s52 s29 s53 s28 s54 s27 s55 s26 s56 s25 s57 s24 s58 s23 s59 s22 bp0 s21 bp1 s20 bp2 s19 bp3 s18 n.c. s17 n.c. s16 n.c. s15 n.c. s14 sda s13 scl s12 clk s11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 013aaa205
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 5 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 6.2 pin description table 3. pin description symbol pin description s31 to s59 1 to 29 lcd segment output 31 to 59 bp0 to bp3 30 to 33 lcd backplane output 0 to 3 n.c. 34 to 37 not connected sda 38 i 2 c-bus serial data input and output scl 39 i 2 c-bus serial clock input clk 40 external clock input and internal clock output v dd 41 supply voltage sync 42 cascade synchronization input and output (active low) osc 43 enable input for internal oscillator a0 to a2 44 to 46 subaddress counter input 0 to 2 sa0 47 i 2 c-bus slave address input 0 v ss 48 ground supply voltage v lcd 49 input of lcd supply voltage s0 to s30 50 to 80 lcd segment output 0 to 30
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 6 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 7. functional description the pcf85134 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 60 segments. the display con?gurations possible with the pcf85134 depend on the number of active backplane outputs required. a selection of display con?gurations is shown in t ab le 4 . all of these con?gurations can be implemented in the typical system shown in figure 3 . the host microprocessor or microcontroller maintains the 2-line i 2 c-bus communication channel with the pcf85134. biasing voltages for the multiplexed lcd waveforms are generated internally, removing the need for an external bias generator. the internal oscillator is selected by connecting pin osc to v ss . the only other connections required to complete the system are the power supplies (pins v dd , v ss and v lcd ) and the lcd panel selected for the application. 7.1 power-on reset (por) at power-on, the pcf85134 resets to the following default starting conditions: ? all backplane outputs are set to v lcd ? all segment outputs are set to v lcd ? the selected drive mode is: 1:4 multiplex with 1 3 bias ? blinking is switched off ? input and output bank selectors are reset table 4. selection of display con?gurations number of 7-segment alphanumeric 14-segment alphanumeric dot matrix backplanes elements digits indicator symbols characters indicator symbols 4 240 30 30 16 16 240 (4 60) 3 180 22 26 12 12 180 (3 60) 2 120 15 15 8 8 120 (2 60) 1 60 7 11 4 4 60 (1 60) fig 3. typical system con?guration host micro- processor/ micro- controller r t r 2c b sda scl osc 60 segment drives 4 backplanes lcd panel (up to 240 elements) pcf85134 a0 a1 a2 sa0 v dd v ss v ss v dd v lcd 013aaa206
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 7 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates ? the i 2 c-bus interface is initialized ? the data pointer and the subaddress counter are cleared (set to logic 0) ? the display is disabled remark: do not transfer data on the i 2 c-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider of three series resistors connected between pins v lcd and v ss . the center resistor is bypassed by switch if the 1 2 bias voltage level for the 1:2 multiplex drive mode con?guration is selected. 7.3 lcd voltage selector the lcd voltage selector coordinates the multiplexing of the lcd in accordance with the selected lcd drive con?guration. the operation of the voltage selector is controlled by the mode-set command (see t ab le 10 ) from the command decoder. the biasing con?gurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of v lcd and the resulting discrimination ratios (d) are given in t ab le 5 . a practical value for v lcd is determined by equating v off(rms) with a de?ned lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode a suitable choice is v lcd >3v th . multiplex drive modes of 1:3 and 1:4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller. bias is calculated by , where the values for a are a = 1 for 1 2 bias a = 2 for 1 3 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 : (1) table 5. biasing characteristics lcd drive mode number of: lcd bias con?guration backplanes levels static 1 2 static 0 1 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 1:3 multiplex 3 4 1 3 0.333 0.638 1.915 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 v off rms () v lcd -------------------------- v on rms () v lcd ------------------------- d v on rms () v off rms () -------------------------- = 1 1a + ------------ - v on rms () a 2 2a n ++ n 1a + () 2 ----------------------------- - v lcd =
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 8 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : (3) using equation 3 , the discrimination for an lcd drive mode of 1:3 multiplex with 1 2 bias is and the discrimination for an lcd drive mode of 1:4 multiplex with 1 2 bias is . the advantage of these lcd drive modes is a reduction of the lcd full scale voltage v lcd as follows: ? 1:3 multiplex ( 1 2 bias): ? 1:4 multiplex ( 1 2 bias): these compare with when 1 3 bias is used. it should be noted that v lcd is sometimes referred as the lcd operating voltage. v off rms () a 2 2a C n + n 1a + () 2 ----------------------------- - v lcd = d v on rms () v off rms () ------------------------ a1 + () 2 n 1 C () + a1 C () 2 n 1 C () + ------------------------------------------- - == 3 1.732 = 21 3 ---------- 1.528 = v lcd 6v off rms () 2.449v off rms ( ) == v lcd 43 () 3 --------------------- - 2.309v off rms () == v lcd 3v off rms () =
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 9 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 7.4 lcd drive mode waveforms 7.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in figure 4 . v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = v lcd . v state2 (t) = v (sn + 1) (t) - v bp0 (t). v off(rms) = 0 v. fig 4. static drive mode waveforms 013aaa207 v ss v lcd v ss v lcd v ss v lcd v lcd - v lcd - v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 10 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 7.4.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the pcf85134 allows the use of 1 2 bias or 1 3 bias in this mode as shown in figure 5 and figure 6 . v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = 0.791v lcd . v state2 (t) = v sn (t) - v bp1 (t). v off(rms) = 0.354v lcd . fig 5. waveforms for the 1:2 multiplex drive mode with 1 2 bias 013aaa208 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd /2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd /2 v lcd /2 v lcd /2 - v lcd - v lcd - v lcd /2 - v lcd /2 sn sn+1 t fr
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 11 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = 0.745v lcd . v state2 (t) = v sn (t) - v bp1 (t). v off(rms) = 0.333v lcd . fig 6. waveforms for the 1:2 multiplex drive mode with 1 3 bias 013aaa209 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd - v lcd 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 s n s n+1 t fr v ss v lcd 2v lcd /3 v lcd /3
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 12 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 7.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies, as shown in figure 7 . v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = 0.638v lcd . v state2 (t) = v sn (t) - v bp1 (t). v off(rms) = 0.333v lcd . fig 7. waveforms for the 1:3 multiplex drive mode with 1 3 bias 013aaa210 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 (a) waveforms at driver. bp2 sn sn+1 sn+2 t fr v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd v ss v lcd 2v lcd /3 v lcd /3
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 13 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 7.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies, as shown in figure 8 . v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = 0.577v lcd . v state2 (t) = v sn (t) - v bp1 (t). v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:4 multiplex drive mode with 1 3 bias 013aaa211 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd 0 v v lcd 2v lcd /3 - 2v lcd /3 v lcd /3 - v lcd /3 - v lcd v ss v lcd 2v lcd /3 v lcd /3
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 14 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 7.5 oscillator the internal logic and the lcd drive signals of the pcf85134 are timed by the frequency f clk , which equals either the built-in oscillator frequency f osc or the external clock frequency f clk(ext) . the clock frequency f clk determines the lcd frame frequency (f fr ). 7.5.1 internal clock the internal oscillator is enabled by connecting pin osc to pin v ss . in this case, the output from pin clk is the clock signal for any cascaded pcf85134 in the system. 7.5.2 external clock connecting pin osc to v dd enables an external clock source. pin clk becomes the external clock input. a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. 7.6 timing and frame frequency the timing of the pcf85134 organizes the internal data ?ow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the synchronization signal ( sync) maintains the correct timing relationship between all the pcf85134 in the system. the timing also generates the lcd frame frequency which is derived as an integer division of the clock frequency (see t ab le 6 ). the frame frequency is a ?xed division of the internal clock or of the frequency applied to pad clk when an external clock is used. 7.7 display register the display register holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship between the data in the display register, the lcd segment outputs, and one column of the display ram. 7.8 segment outputs the lcd drive section includes 60 segment outputs (s0 to s59) which must be connected directly to the lcd. the segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. when less than 60 segment outputs are required the unused segment outputs must be left open-circuit. table 6. lcd frame frequencies frame frequency nominal frame frequency (hz) 82 f fr f clk 24 --------- =
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 15 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 7.9 backplane outputs the lcd drive section includes four backplane outputs: bp0 to bp3. the backplane output signals are generated based on the selected lcd drive mode. ? in 1:4 multiplex drive mode: bp0 to bp3 must be connected directly to the lcd. if less than four backplane outputs are required the unused outputs can be left open-circuit. ? in 1:3 multiplex drive mode: bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. ? in 1:2 multiplex drive mode: bp0 and bp2, bp1 and bp3 respectively carry the same signals and can also be paired to increase the drive capabilities. ? in static drive mode: the same signal is carried by all four backplane outputs; and they can be connected in parallel for very high drive requirements. 7.10 display ram the display ram is a static 60 4 bit ram which stores lcd data. a logic 1 in the ram bit map indicates the on-state of the corresponding lcd element; similarly, a logic 0 indicates the off-state. there is a one-to-one correspondence between the ram addresses and the segment outputs and between the individual bits of a ram word and the backplane outputs. the display ram bit map, figure 9 , shows rows 0 to 3 which correspond with the backplane outputs bp0 to bp3, and columns 0 to 59 which correspond with the segment outputs s0 to s59. in multiplexed lcd applications the segment data of the ?rst, second, third, and fourth row of the display ram are time-multiplexed with bp0, bp1, bp2, and bp3 respectively. when display data is transmitted to the pcf85134, the received display bytes are stored in the display ram in accordance with the selected lcd drive mode. the data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples. to illustrate the ?lling order, an example of a 7-segment display showing all drive modes is given in figure 10 ; the ram ?lling organization depicted applies equally to other lcd types. the display ram bit map shows the direct relationship between the display ram addresses and the segment outputs and between the bits in a ram word and the backplane outputs. fig 9. display ram bit map 0 0 1 2 3 1 2 3 4 55 56 57 58 59 display ram addresses/segment outputs (s) display ram rows/ backplane outputs (bp) 013aaa212 columns rows
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 16 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates x = data bit unchanged. fig 10. relationship between lcd layout, drive mode, display ram storage order and display data transmitted over the i 2 c-bus 001aaj646 acbdpf egd msb lsb bdpcadgfe msb lsb abfgecddp msb lsb cba f geddp msb lsb drive mode static 1:2 multiplex 1:3 multiplex 1:4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte bp0 bp0 bp1 bp0 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 rows display ram rows/backplane outputs (bp) byte1 columns display ram address/segment outputs (s) n a b x x 0 1 2 3 f g x x e c x x d dp x x n + 1 n + 2 n + 3 byte1 byte2 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n b dp c x 0 1 2 3 a d g x f e x x n + 1 n + 2 byte1 byte2 byte3 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n + 1 n a c b dp 0 1 2 3 f e g d byte1 byte2 byte3 byte4 byte5 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) s n+2 s n+3 s n+1 s n dp a f b g e c d s n+2 s n+1 s n+7 s n s n+3 s n+5 s n+6 s n+4 dp a f b g e c d s n s n+1 s n+2 dp a f b g e c d s n+1 s n dp a f b g e c d
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 17 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates the following applies to figure 10 : ? in static drive mode the eight transmitted data bits are placed into row 0 of eight successive 4-bit ram words. ? in 1:2 multiplex mode the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit ram words. ? in 1:3 multiplex mode the eight bits are placed in triples into row 0, 1, and 2 of three successive 4-bit ram words, with bit 3 of the third address left unchanged. it is not recommended to use this bit in a display because of the dif?cult addressing. this last bit may, if necessary, be controlled by an additional transfer to this address, but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. ? in the 1:4 multiplex mode the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 of two successive 4-bit ram words. 7.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the data pointer by the load-data-pointer command (see t ab le 9 ). following this command, an arriving data byte is stored at the display ram address indicated by the data pointer. the ?lling order is shown in figure 10 . after each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected lcd drive mode: ? in static drive mode by eight. ? in 1:2 multiplex drive mode by four. ? in 1:3 multiplex drive mode by three. ? in 1:4 multiplex drive mode by two. if an i 2 c-bus data access terminates early, the state of the data pointer is unknown. consequently, the data pointer must be rewritten prior to further ram accesses. 7.12 subaddress counter the storage of display data is conditioned by the content of the subaddress counter. storage is allowed only when the content of the subaddress counter match with the hardware subaddress applied to a0, a1 and a2. the subaddress counter value is de?ned by the device-select command (see t ab le 12 ). if the content of the subaddress counter and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had taken place. the subaddress counter is also incremented when the data pointer over?ows. in cascaded applications each pcf85134 in the cascade must be addressed separately. initially, the ?rst pcf85134 is selected by sending the device-select command matching the ?rst device's hardware subaddress. then the data pointer is set to the preferred display ram address by sending the load-data-pointer command.
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 18 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates once the display ram of the ?rst pcf85134 has been written, the second pcf85134 is selected by sending the device-select command again. this time however the command matches the second device's hardware subaddress. next the load-data-pointer command is sent to select the preferred display ram address of the second pcf85134. this last step is very important because during writing data to the ?rst pcf85134, the data pointer of the second pcf85134 is incremented. in addition, the hardware subaddress should not be changed whilst the device is being accessed on the i 2 c-bus interface. 7.13 output bank selector the output bank selector (see t ab le 13 ) selects one of the four rows per display ram address for transfer to the display register. the actual row selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode, all ram addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 ? in 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially ? in 1:2 multiplex mode, rows 0 and 1 are selected ? in static mode, row 0 is selected the sync signal resets these sequences to the following starting points: bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex, and bit 0 for static mode. the pcf85134 includes a ram bank switching feature in the static and 1:2 multiplex drive modes. in the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. in the 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it, once it is assembled. 7.14 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive con?guration. display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. the input bank selector functions independently to the output bank selector. 7.15 blinker the display blink capabilities of the pcf85134 are very versatile. the whole display can blink at frequencies selected by the blink-select command (see t ab le 14 ). the blink frequencies are fractions of the clock frequency. the ratios between the clock and blink frequencies depend on the blink mode selected (see t ab le 7 ).
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 19 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates an additional feature is for an arbitrary selection of lcd segments to blink. this applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. by means of the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blink frequency. this mode can also be speci?ed by the blink-select command. in the 1:3 and 1:4 multiplex modes, where no alternate ram bank is available, groups of lcd segments can blink by selectively changing the display ram data at ?xed time intervals. the entire display can blink at a frequency other then the nominal blink frequency. this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode-set command (see t ab le 10 ). table 7. blink frequencies blink mode operating mode ratio blink frequency with respect to f clk (typical) unit f clk = 1.970 khz off - blinking off hz 1 2.5 hz 2 1.3 hz 3 0.6 hz f clk 768 --------- f clk 1536 ----------- - f clk 3072 ----------- -
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 20 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 8. basic architecture 8.1 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. bit transfer is illustrated in figure 11 . 8.1.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low change of the data line, while the clock is high, is de?ned as the start condition (s). a low-to-high change of the data line, while the clock is high, is de?ned as the stop condition (p). the start and stop conditions are illustrated in figure 12 . 8.1.2 system con?guration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves. the system con?guration is shown in figure 13 . fig 11. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 12. de?nition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 21 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 8.1.3 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. ? a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 14 . fig 13. system con?guration mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig 14. acknowledgement of the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 22 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 8.1.4 i 2 c-bus controller the pcf85134 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pcf85134 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, the transferred command data and the hardware subaddress. in single device applications, the hardware subaddress inputs a0, a1, and a2 are normally tied to v ss which de?nes the hardware subaddress 0. in multiple device applications a0, a1, and a2 are tied to v ss or v dd using a binary coding scheme, so that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 8.1.5 input ?lters to enhance noise immunity in electrically adverse environments, rc low-pass ?lters are provided on the sda and scl lines. 8.2 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are reserved for the pcf85134. the least signi?cant bit of the slave address is bit r/ w. the pcf85134 is a write-only device. it will not respond to a read access, so this bit should always be logic 0. the second bit of the slave address is de?ned by the level tied at input sa0. two displays controlled by pcf85134 can be recognized on the same i 2 c-bus which allows: ? up to 16 pcf85134s on the same i 2 c-bus for very large lcd applications ? the use of two types of lcd multiplex drive mode on the same i 2 c-bus the i 2 c-bus protocol is shown in figure 15 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the available pcf85134 slave addresses. all pcf85134s with the same sa0 level acknowledge in parallel to the slave address. all pcf85134s with the alternative sa0 level ignore the whole i 2 c-bus transfer.
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 23 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates after acknowledgement, the control byte is sent de?ning if the next byte is a ram or command information. the control byte also de?nes if the next byte is a control byte or further ram or command data (see figure 16 and t ab le 8 ). in this way it is possible to con?gure the device and then ?ll the display ram with little overhead. the command bytes and control bytes are also acknowledged by all addressed pcf85134s connected to the bus. the display bytes are stored in the display ram at the address speci?ed by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated. fig 15. i 2 c-bus protocol examples a) transmit two bytes of ram data mgl752 s a 0 s 01110 0 0 control byte slave address ram/command byte ram data m s b l s b a a p r/w = 0 s a 0 s 01110 0 01 0 a a a p ram data a b) transmit two command bytes command s a 0 s 01110 0 10 0 a a a p command a a c) transmit one command byte and two ram date bytes command s a 0 s 01110 0 10 00 01 0 a a a p ram data a ram data a a c o r s fig 16. control byte format table 8. control byte description bit symbol value description 7co continue bit 0 last control byte 1 control bytes continue 6rs register selection 0 command register 1 data register 5 to 0 - not relevant mgl753 not relevant co 76 543210 rs msb lsb
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 24 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates the acknowledgement after each byte is made only by the (a0, a1, and a2) addressed pcf85134. after the last display byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be issued to restart i 2 c-bus access. 8.3 command decoder the command decoder identi?es command bytes that arrive on the i 2 c-bus. there are ?ve commands: [1] the possibility to disable the display allows implementation of blinking under external control. table 9. de?nition of commands command operation code reference bit 7 6 5 4 3 2 1 0 mode-set 1 100eb m[1:0] t ab le 10 load-data-pointer 0 p[6:0] t ab le 11 device-select 1 1100 a[2:0] t ab le 12 bank-select 1 11110i o t ab le 13 blink-select 1 1110a bf[1:0] t ab le 14 table 10. mode-set command bit description bit symbol value description 7 to 4 - 1100 ?xed value 3e display status 0 disabled (blank) [1] 1 enable 2b lcd bias con?guration 0 1 3 bias 1 1 2 bias 1 to 0 m[1:0] lcd drive mode selection 01 static; 1 backplane 10 1:2 multiplex; 2 backplanes 11 1:3 multiplex; 3 backplanes 00 1:4 multiplex; 4 backplanes table 11. load-data-pointer command bit description see section 7.11 . bit symbol value description 7 - 0 ?xed value 6 to 0 p[6:0] 0000000 to 0111011 7-bit binary value of 0 to 59 table 12. device-select command bit description see section 7.12 . bit symbol value description 7 to 3 - 11100 ?xed value 2 to 0 a[2:0] 000 to 111 3-bit binary value of 0 to 7
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 25 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates [1] the bank-select command has no effect in 1:3 or 1:4 multiplex drive modes. [1] normal blinking can only be selected in multiplex drive mode 1:3 or 1:4. [2] for the blink frequencies, see t ab le 7 . 8.4 display controller the display controller executes the commands identi?ed by the command decoder. it contains the status registers of the pcf85134 and coordinates their effects. the controller also loads display data into the display ram as required by the storage order. table 13. bank-select command bit description see section 7.10 , section 7.11 , section 7.12 , section 7.13 and section 7.14 . bit symbol value description static 1:2 multiplex [1] 7 to 2 - 111110 ?xed value 1i input bank selection : storage of arriving display data 0 ram row 0 ram rows 0 and 1 1 ram row 2 ram rows 2 and 3 0o output bank selection : retrieval of lcd display data 0 ram row 0 ram rows 0 and 1 1 ram row 2 ram rows 2 and 3 table 14. blink-select command bit description see section 7.15 . bit symbol value description 7 to 3 - 11110 ?xed value 2a blink mode selection 0 normal blinking [1] 1 blinking by alternating display ram banks 1 to 0 bf[1:0] blink frequency selection 00 off 01 1 10 2 11 3
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 26 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 9. internal circuitry fig 17. device protection diagram sa0 v dd v dd v ss v ss v lcd v ss sda 001aah615 v ss scl v ss clk v dd v ss osc v dd v ss sync v dd v ss a0, a1, a2 v dd v ss bp0, bp1, bp2, bp3 v lcd v ss s0 to s59 v lcd v ss
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 27 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 10. limiting values [1] stresses above these values listed may cause permanent damage to the device. [2] pins sda, scl, clk, sync, sa0, osc and a0 to a2. [3] pins s0 to s59 and bp0 to bp3. [4] hbm: human body model, according to ref . 5 jesd22-a114 . [5] mm: machine model, according to ref . 6 jesd22-a115 . [6] pass level; latch-up testing according to ref . 7 jesd78 at maximum ambient temperature (t amb(max) = +85 c). [7] according to the nxp store and transport requirements (see ref . 9 nx3-00092 ) the devices have to be stored at a temperature of +8 cto+45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to avoid such artifacts, v lcd and v dd must be applied or removed together. table 15. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.5 v i dd supply current - 50 +50 ma v lcd lcd supply voltage - 0.5 +7.5 v i dd(lcd) lcd supply current - 50 +50 ma i ss ground supply current - 50 +50 ma v i input voltage [2] - 0.5 +6.5 v i i input current [2] - 10 +10 ma v o output voltage [2] - 0.5 +6.5 v [3] - 0.5 +7.5 v i o output current [2] [3] - 10 +10 ma p tot total power dissipation - 400 mw p/out power dissipation per output - 100 mw v esd electrostatic discharge voltage hbm [4] - 2500 v mm [5] - 200 v i lu latch-up current [6] - 200 ma t stg storage temperature [7] - 65 +150 c
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 28 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 11. static characteristics [1] lcd outputs are open-circuit; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [2] not tested, design speci?cation only. [3] c bpl = backplane capacitance. [4] measured on sample basis only. [5] c sgm = segment capacitance. table 16. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage 2.5 - 6.5 v i dd supply current f clk(ext) = 1536 hz [1] -820 m a i dd(lcd) lcd supply current f clk(ext) = 1536 hz [1] -2460 m a logic v i input voltage v ss - 0.5 - v dd + 0.5 v v il low-level input voltage on pins clk, sync, osc, a0 to a2 and sa0 v ss - 0.3v dd v v ih high-level input voltage on pins clk, sync, osc, a0 to a2 and sa0 0.7v dd -v dd v v por power-on reset voltage 1.0 1.3 1.6 v i ol low-level output current output sink current; v ol = 0.4 v; v dd = 5 v; on pins clk and sync 1-- ma i oh high-level output current output source current; v oh = 4.6 v; v dd = 5 v; on pin clk 1-- ma i l leakage current v i = v dd or v ss ; on pins sa0, a0 to a2 and clk - 1-+1 m a v i = v dd ; on pin osc - 1-+1 m a c i input capacitance [2] --7pf i 2 c-bus; pins sda and scl v i input voltage v ss - 0.5 - 5.5 v v il low-level input voltage pin scl v ss - 0.3v dd v pin sda v ss - 0.2v dd v v ih high-level input voltage 0.7v dd - 5.5 v i ol low-level output current output sink current; v ol = 0.4 v; v dd = 5 v; on pin sda 3-- ma i l leakage current v i = v dd or v ss - 1-+1 m a c i input capacitance [2] --7pf lcd outputs output pins bp0 to bp3 v bp voltage on pin bp c bpl = 35 nf [3] - 100 - +100 mv r bp resistance on pin bp v lcd = 5 v [4] - 1.5 10 k w output pins s0 to s59 v s voltage on pin s c sgm = 35 nf [5] - 100 - +100 mv r s resistance on pin s v lcd = 5 v [4] - 6.0 13.5 k w
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 29 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 12. dynamic characteristics [1] typical output (duty cycle d = 50 %). [2] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . table 17. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit clock internal: output pin clk f osc oscillator frequency v dd = 5 v [1] 1440 1970 2640 hz external: input pin clk f clk(ext) external clock frequency v dd = 5 v 800 - 3600 hz t clk(h) high-level clock time 130 - - m s t clk(l) low-level clock time 130 - - m s synchronization: input pin sync t pd(sync_n) sync propagation delay - 30 - ns t sync_nl sync low time 1 - - m s outputs: pins bp0 to bp3 and s0 to s59 t pd(drv) driver propagation delay v lcd = 5 v - - 30 m s i 2 c-bus: timing [2] pin scl f scl scl frequency - - 400 khz t low low period of the scl clock 1.3 - - m s t high high period of the scl clock 0.6 - - m s pin sda t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns pins scl and sda t buf bus free time between a stop and start condition 1.3 - - m s t su;sto set-up time for stop condition 0.6 - - m s t hd;sta hold time (repeated) start condition 0.6 - - m s t su;sta set-up time for a repeated start condition 0.6 - - m s t r rise time of both sda and scl signals - - 0.3 m s t f fall time of both sda and scl signals - - 0.3 m s c b capacitive load for each bus line - - 400 pf t w(spike) spike pulse width - - 50 ns
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 30 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates fig 18. driver timing waveforms fig 19. i 2 c-bus timing waveforms 001aah618 0.7v dd 0.3v dd 0.7v dd 0.3v dd 1 / f clk t pd(sync_n) t pd(sync_n) t clk(h) t clk(l) sync clk 0.5 v 0.5 v t pd(drv) bp0 to bp3, and s0 to s59 t sync_nl (v dd = 5 v) sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 31 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 13. application information 13.1 cascaded operation large display con?gurations of up to 16 pcf85134 can be recognized on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1, and a2) and the programmable i 2 c-bus slave address (sa0). when cascaded pcf85134 are synchronized, they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other pcf85134 of the cascade contribute additional segment outputs, but their backplane outputs are left open-circuit (see figure 20 ). table 18. addressing cascaded pcf85134 cluster bit sa0 pin a2 pin a1 pin a0 device 100000 0011 0102 0113 1004 1015 1106 1117 210008 0019 01010 01111 10012 10113 11014 11115
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 32 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates the sync line is provided to maintain the correct synchronization between all cascaded pcf85134. synchronization is guaranteed after a power-on reset. the only time that sync is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by de?ning a multiplex drive mode when pcf85134 with different sa0 levels are cascaded). sync is organized as an input/output pin. the output selection is realized as an open-drain driver with an internal pull-up resistor. a pcf85134 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. if synchronization in the cascade is lost, it is restored by the ?rst pcf85134 to assert sync. the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the pcf85134 are shown in figure 21 . fig 20. cascaded pcf85134 con?guration host micro- processor/ micro- controller sda scl clk osc sync 60 segment drives 4 backplanes 60 segment drives lcd panel pcf85134 a0 a1 a2 sa0 v ss v ss v ss v dd v dd v lcd v lcd v dd v lcd 013aaa213 sda scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 a2 sa0 pcf85134 bp0 to bp3 r t r 2c b
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 33 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates the contact resistance between the sync pins of cascaded devices must be controlled. if the resistance is too high, the device will not be able to synchronize properly. t ab le 19 shows the maximum contact resistance values. fig 21. synchronization of the cascade for various pcf85134 drive modes table 19. sync contact resistance number of devices maximum contact resistance 2 6000 w 3 to 5 2200 w 6 to 10 1200 w 11 to 16 700 w t fr = f fr 1 bp0 sync bp0 (1/2 bias) sync bp0 (1/3 bias) (a) static drive mode. (b) 1:2 multiplex drive mode. (c) 1:3 multiplex drive mode. (d) 1:4 multiplex drive mode. bp0 (1/3 bias) sync sync bp0 (1/3 bias) mgl755
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 34 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 14. package outline fig 22. package outline sot315-1 (lqfp80) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 35 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 15. handling information all input and output pins are protected against electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 36 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities 16.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 23 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 20 and 21 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 23 . table 20. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 21. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 37 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 17. abbreviations msl: moisture sensitivity level fig 23. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 22. abbreviations acronym description cmos complementary metal-oxide semiconductor esd electrostatic discharge hbm human body model ic integrated circuit lcd liquid crystal display mm machine model ram random access memory
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 38 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 18. references [1] an10365 surface mount re?ow soldering description [2] iec 60134 rating systems for electronic tubes and valves and analogous semiconductor devices [3] iec 61340-5 protection of electronic devices from electrostatic phenomena [4] ipc/jedec j-std-020d moisture/re?ow sensitivity classi?cation for nonhermetic solid state surface mount devices [5] jesd22-a114 electrostatic discharge (esd) sensitivity testing human body model (hbm) [6] jesd22-a115 electrostatic discharge (esd) sensitivity testing machine model (mm) [7] jesd78 ic latch-up test [8] jesd625-a requirements for handling electrostatic-discharge-sensitive (esds) devices [9] nx3-00092 nxp store and transport requirements [10] snv-fa-01-02 marking formats integrated circuits [11] um10204 i 2 c-bus speci?cation and user manual 19. revision history table 23. revision history document id release date data sheet status change notice supersedes pcf85134_1 20091217 product data sheet - -
pcf85134_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 17 december 2009 39 of 40 nxp semiconductors pcf85134 universal lcd driver for low multiplex rates 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 20.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 20.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 20.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pcf85134 universal lcd driver for low multiplex rates ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 17 december 2009 document identifier: pcf85134_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 power-on reset (por) . . . . . . . . . . . . . . . . . . 6 7.2 lcd bias generator. . . . . . . . . . . . . . . . . . . . . . 7 7.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 lcd drive mode waveforms . . . . . . . . . . . . . . . 9 7.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 7.4.2 1:2 multiplex drive mode . . . . . . . . . . . . . . . . . 10 7.4.3 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . 12 7.4.4 1:4 multiplex drive mode . . . . . . . . . . . . . . . . . 13 7.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.1 internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 timing and frame frequency . . . . . . . . . . . . . . 14 7.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 7.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 15 7.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.11 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.12 subaddress counter . . . . . . . . . . . . . . . . . . . . 17 7.13 output bank selector. . . . . . . . . . . . . . . . . . . . 18 7.14 input bank selector . . . . . . . . . . . . . . . . . . . . . 18 7.15 blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 basic architecture . . . . . . . . . . . . . . . . . . . . . . 20 8.1 characteristics of the i 2 c-bus . . . . . . . . . . . . . 20 8.1.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1.1.1 start and stop conditions . . . . . . . . . . . . . 20 8.1.2 system con?guration . . . . . . . . . . . . . . . . . . . 20 8.1.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1.4 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 22 8.1.5 input ?lters . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.2 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22 8.3 command decoder . . . . . . . . . . . . . . . . . . . . . 24 8.4 display controller . . . . . . . . . . . . . . . . . . . . . . 25 9 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 11 static characteristics. . . . . . . . . . . . . . . . . . . . 28 12 dynamic characteristics . . . . . . . . . . . . . . . . . 29 13 application information. . . . . . . . . . . . . . . . . . 31 13.1 cascaded operation . . . . . . . . . . . . . . . . . . . . 31 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 34 15 handling information . . . . . . . . . . . . . . . . . . . 35 16 soldering of smd packages . . . . . . . . . . . . . . 35 16.1 introduction to soldering. . . . . . . . . . . . . . . . . 35 16.2 wave and re?ow soldering . . . . . . . . . . . . . . . 35 16.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 36 16.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 36 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 38 20 legal information . . . . . . . . . . . . . . . . . . . . . . 39 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 39 20.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 39 21 contact information . . . . . . . . . . . . . . . . . . . . 39 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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